The present invention generally relates to methods of increasing the etch rate of a deep silicon dry etch and, in particular, relates to a method of increasing the etch rate during a deep silicon dry etch by altering the geometric shape of the etch mask.
Conductive passageways, or vias, formed through silicon semiconductor wafers provide a way to transmit power and signals from one side of the silicon semiconductor wafer to the other side. Silicon semiconductors containing vias are used in a variety of technologies, from imaging products and memory to high-speed logic and processing applications. One emerging technology that relies heavily on vias formed through silicon semiconductor wafers is three dimensional (3D) integrated circuit (IC). 3D ICs are created by stacking of thinned semiconductor wafer chips and interconnecting them with through-silicon vias (TSVs). One advantage of using 3D ICs is that memory devices and image sensors can be made without lead frames and substrates, thereby reducing wafer-level packaging costs. Packing costs are estimated to range between fifteen to twenty-five percent of the cost of the finished product. Additionally, single silicon semiconductor wafers can also use vias, for example, to connect ground on one side of the wafer to the other side of the wafer which is connected to a lead frame. Other examples of semiconductor wafer technologies employing the use of vias are DRAM, imagers and Flash memory.
Typically, the etch rate of silicon is directly related to the amount of silicon exposed in an etch mask. However, it can be beneficial to increase the etch rate of some areas of exposed silicon while maintaining the typical etch rate in other areas in order to etch one via deeper than another. Additionally, it could be beneficial to simply increase the overall etch rate of the entire process for increasing production and manufacturability.
Therefore, there is a need to have differing etch rates between different areas of the silicon wafer that have the same amount of exposed silicon in the etch mask.
There is another need to increase the overall etch rate of the exposed silicon over the entire area of the silicon wafer.
There is yet another need to control the depth of the vias that are dry etched in the silicon wafer
There is still another need to have vias with virtually the same size diameter have differing depths on a silicon wafer.